Nonvolatile semiconductor memory device having grooves isolating the floating electrodes of memory cells and method of manufacturing the nonvolatile semiconductor memory device

ABSTRACT

A plurality of nonvolatile memory elements formed on element regions respectively isolated by element isolation regions on a main surface of a first conductive type semiconductor substrate, the nonvolatile semiconductor memory elements comprising a gate insulating film formed on the main surface of the semiconductor substrate, a plurality of floating electrodes formed along a first direction on the gate insulating film, a plurality of grooves formed among the plurality of floating electrodes, groove insulating films filled in the plurality of the grooves, a second conductive type impurity diffusion region formed along a second direction so as to sandwich the floating electrodes, interelectrode insulating films formed along the first direction on the plurality of floating electrodes and the groove insulating films, and control electrodes formed on the interelectrode insulating films.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2003-107991, filed Apr. 11,2003, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memorydevice and a method of manufacturing the same, and more specifically, isapplied to a nonvolatile semiconductor memory device having groovesinsulated by insulating films between floating electrodes of adjacentnonvolatile memory elements, and to a method of manufacturing the same.

2. Description of the Related Art

As a conventional nonvolatile semiconductor memory device havingfloating electrodes, there is a device as shown in FIG. 17 (for example,Jpn. Pat. Appln. KOKAI Publication No. P2002-016154). The nonvolatilesemiconductor memory device shown in FIG. 17 comprises a siliconsubstrate 111, a gate oxide film 112, a first polycrystalline siliconfilm 113 which is a lower layer floating electrode, a silicon oxide film116, a silicon oxide film 117 which is an STI filling material for anelement isolation region, a second polycrystalline silicon film 118which is an upper layer floating electrode, an ONO insulating film (athree-layer film of a silicon oxide film, a silicon nitride film, and asilicon oxide film) 119, a third polycrystalline silicon film 120 whichis a lower layer control electrode, a WSi film 121 which is an upperlayer control electrode, and a silicon oxide film 122 which is aninsulating protective film.

The first polycrystalline silicon film 113 which is the lower layerfloating electrode is insulated from the lower floating electrode, towhich a cell which is adjacent thereto corresponds, by the silicon oxidefilms 116, 117 at the element isolation region. The secondpolycrystalline silicon film 118 which is the upper layer floatingelectrode is isolated from the upper floating electrode, to which a cellwhich is adjacent thereto corresponds, by a groove 126 on the siliconoxide film 117. The floating electrode 118 and the control electrode 120are isolated by the ONO insulating film 119 which is an interelectrodeinsulating film.

However, the conventional nonvolatile semiconductor memory device isstructured such that the control electrode 120 along with the ONOinsulating film 119 enters the interior of the groove 126 between theadjacent cells at this floating electrode corner portion 125.

Therefore, electric fields converge at the floating electrode cornerportion 125, and the insulating characteristic of the ONO insulatingfilm 119 at this corner portion 125 deteriorates. Thus, there is theproblem that the characteristic of maintaining the electric chargesinjected in the floating electrodes 113, 118 in accordance with storedinformation is poor.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided anonvolatile semiconductor memory device comprising:

a plurality of nonvolatile memory elements formed on element regionsrespectively isolated by element isolation regions on a main surface ofa first conductive type semiconductor substrate;

the nonvolatile semiconductor memory elements comprising:

a gate insulating film formed on the main surface of the semiconductorsubstrate;

a plurality of floating electrodes formed along a first direction on thegate insulating film;

a plurality of grooves formed among the plurality of floatingelectrodes;

groove insulating films filled in the plurality of the grooves;

a second conductive type impurity diffusion region formed along a seconddirection so as to sandwich the floating electrodes;

interelectrode insulating films formed along the first direction on theplurality of floating electrodes and the groove insulating films; and

control electrodes formed on the interelectrode insulating films.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a cross-sectional structural view in which a cross-sectionalstructure of a nonvolatile semiconductor memory device having floatingelectrodes according to a first embodiment of the present invention iscut along line 1-1 of FIG. 3, and is viewed in the direction of thearrow;

FIG. 2 is a cross-sectional structural view in which a cross-sectionalstructure of the nonvolatile semiconductor memory device having thefloating electrodes according to the first embodiment of the presentinvention is cut along line 2-2 of FIG. 3, and is viewed in thedirection of the arrow;

FIG. 3 is a plan view schematically showing a layout of the nonvolatilesemiconductor memory device having the floating electrodes according tothe first embodiment of the present invention;

FIG. 4 is a graph showing the groove width/film thickness dependency ofan electric charge maintaining characteristic defective rate accordingto the first embodiment of the present invention;

FIG. 5A is a first process view for explanation, with respect to thecross-sectional structure shown in FIG. 1, of one example of a method ofmanufacturing the nonvolatile semiconductor memory device according tothe first embodiment of the present invention;

FIG. 5B is a second process view for explanation, with respect to thecross-sectional structure shown in FIG. 1, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 5C is a third process view for explanation, with respect to thecross-sectional structure shown in FIG. 1, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 5D is a fourth process view for explanation, with respect to thecross-sectional structure shown in FIG. 1, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 6A is a first process view for explanation, with respect to thecross-sectional structure shown in FIG. 2, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 6B is a second process view for explanation, with respect to thecross-sectional structure shown in FIG. 2, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 6C is a third process view for explanation, with respect to thecross-sectional structure shown in FIG. 2, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 6D is a fourth process view for explanation, with respect to thecross-sectional structure shown in FIG. 2, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 6E is a fifth process view for explanation, with respect to thecross-sectional structure shown in FIG. 2, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention;

FIG. 7 is a cross-sectional structural view of a nonvolatilesemiconductor memory device having floating electrodes according to asecond embodiment of the present invention;

FIG. 8A is a first process view for explanation, with respect to thecross-sectional structure shown in FIG. 7, of one example of a method ofmanufacturing the nonvolatile semiconductor memory device according tothe second embodiment of the present invention;

FIG. 8B is a second process view for explanation, with respect to thecross-sectional structure shown in FIG. 7, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the second embodiment of the present invention;

FIG. 8C is a third process view for explanation, with respect to thecross-sectional structure shown in FIG. 7, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the second embodiment of the present invention;

FIG. 9 is a cross-sectional structural view of a nonvolatilesemiconductor memory device having floating electrodes according to athird embodiment of the present invention;

FIG. 10A is a first process view for explanation, with respect to thecross-sectional structure shown in FIG. 9, of one example of a method ofmanufacturing the nonvolatile semiconductor memory device according tothe third embodiment of the present invention;

FIG. 10B is a second process view for explanation, with respect to thecross-sectional structure shown in FIG. 9, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the third embodiment of the present invention;

FIG. 10C is a third process view for explanation, with respect to thecross-sectional structure shown in FIG. 9, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the third embodiment of the present invention;

FIG. 11 is a cross-sectional structural view of a nonvolatilesemiconductor memory device having floating electrodes according to afourth embodiment of the present invention;

FIG. 12A is a first process view for explanation, with respect to thecross-sectional structure shown in FIG. 11, of one example of a methodof manufacturing the nonvolatile semiconductor memory device accordingto the fourth embodiment of the present invention;

FIG. 12B is a second process view for explanation, with respect to thecross-sectional structure shown in FIG. 11, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the fourth embodiment of the present invention;

FIG. 12C is a third process view for explanation, with respect to thecross-sectional structure shown in FIG. 11, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the fourth embodiment of the present invention;

FIG. 13 is a cross-sectional structural view of a nonvolatilesemiconductor memory device having floating electrodes according to afifth embodiment of the present invention;

FIG. 14A is a first process view for explanation, with respect to thecross-sectional structure shown in FIG. 13, of one example of a methodof manufacturing the nonvolatile semiconductor memory device accordingto the fifth embodiment of the present invention;

FIG. 14B is a second process view for explanation, with respect to thecross-sectional structure shown in FIG. 13, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the fifth embodiment of the present invention;

FIG. 14C is a third process view for explanation, with respect to thecross-sectional structure shown in FIG. 13, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the fifth embodiment of the present invention;

FIG. 14D is a fourth process view for explanation, with respect to thecross-sectional structure shown in FIG. 13, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the fifth embodiment of the present invention;

FIG. 15 is a cross-sectional structural view of a nonvolatilesemiconductor memory device having floating electrodes according to asixth embodiment of the present invention;

FIG. 16A is a first process view for explanation, with respect to thecross-sectional structure shown in FIG. 15, of one example of a methodof manufacturing the nonvolatile semiconductor memory device accordingto the sixth embodiment of the present invention;

FIG. 16B is a second process view for explanation, with respect to thecross-sectional structure shown in FIG. 15, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the sixth embodiment of the present invention;

FIG. 16C is a third process view for explanation, with respect to thecross-sectional structure shown in FIG. 15, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the sixth embodiment of the present invention;

FIG. 16D is a fourth process view for explanation, with respect to thecross-sectional structure shown in FIG. 15, of one example of the methodof manufacturing the nonvolatile semiconductor memory device accordingto the sixth embodiment of the present invention; and

FIG. 17 is a cross-sectional structural view of a conventionalnonvolatile semiconductor memory device having floating electrodesaccording to the prior art.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments in which the present invention is applied to anonvolatile semiconductor memory device which is formed on the mainsurface of a silicon substrate and which has floating electrodes will bedescribed with reference to the drawings. Note that, in thisdescription, portions which are common to all drawings are denoted bycommon reference numerals.

FIRST EMBODIMENT

Hereinafter, a nonvolatile semiconductor memory device having floatingelectrodes according to a first embodiment of the present invention willbe described by using FIGS. 1 to 3. Here, FIG. 1 is a cross-sectionalstructural view in which the plan view of FIG. 3 is cut along line 1-1and which is viewed in the direction of the arrow. FIG. 2 is across-sectional structural view in which the plan view of FIG. 3 is cutalong line 2-2 and which is viewed in the direction of the arrow. FIG. 3is a plan view of the nonvolatile semiconductor memory device accordingto the first embodiment of the present invention.

As shown in FIG. 1, a silicon oxide film 12 which will be a gateinsulating film and a polycrystalline silicon film 13 which will be afirst floating electrode layer are successively laminated in a state ofbeing isolated by a silicon oxide film 16 formed in the interior of anSTI groove 17A forming an element isolation region. A silicon oxide film17, which is an STI filling material is filled in the interior of theSTI groove 17A surrounded by the silicon oxide film 16.

A polycrystalline silicon film 18 is formed as a second floatingelectrode layer on the polycrystalline silicon film 13. Thepolycrystalline silicon film 18 is isolated by a groove 18A at asubstantially central portion of the top surface of the silicon oxidefilm 17 which is the STI filling material. In the groove 18A and on thepolycrystalline silicon oxide film 18 which will be the second floatingelectrode film, an ONO insulating film (formed of three layers of asilicon oxide film, a silicon nitride film, and a silicon oxide film)19-1 is deposited as an interelectrode insulating film.

On the ONO insulating film 19-1, a polycrystalline silicon film 20 whichwill be a first control electrode layer and a WSi film 21 which will bea second control electrode layer are successively formed. As shown inFIG. 3, control electrodes CG<0>, CG<1> are formed by these first andsecond control electrode layers 20, 21.

As shown in FIGS. 2 and 3, on the main surface of the silicon substrate11, the silicon oxide film 12 which will be the gate insulating film andthe polycrystalline silicon film 13 which will be the first floatingelectrode layer are formed at the element region isolated by the siliconoxide film 17. In the interior of the silicon substrate 11 beneath thesilicon oxide film 12, impurity diffusion layers 24-1, 24-2, 24-3 whichwill be source regions/drain regions are formed so as to extend betweenthe adjacent polycrystalline silicon films 13.

The polycrystalline silicon film 18 is formed on the polycrystallinesilicon film 13 as the second floating electrode layer. On thispolycrystalline silicon film 18, the ONO insulating film (formed ofthree layers of a silicon oxide film, a silicon nitride film, and asilicon oxide film) 19-1 is deposited as an interelectrode insulatingfilm. The polycrystalline silicon film 13 and polycrystalline siliconfilm 18 respectively structure two-layer structure floating electrodesFG<01>, FG<11> at nonvolatile memory elements MC<01>, MC<11> which areadjacent to one another.

The polycrystalline silicon film 20 which will be the first controlelectrode layer and the WSi film 21 which will be the second controlelectrode layer are successively formed on the ONO insulating film 19-1.In the same way, the control electrodes CG<0>, CG<1> of the adjacent twononvolatile memory elements MC<01>, MC<11> are formed by these first andsecond control electrode layers 20, 21. A gate wall insulating film 23is formed at the side faces of the nonvolatile memory elements MC<01> toMC<11> having them, and silicon oxide films 22 are respectively formedon the top surfaces thereof.

Here, a plan view layout of the nonvolatile semiconductor memory deviceof the embodiment having the cross-sectional structure shown in FIGS. 1and 2 will be described with reference to the plan view of FIG. 3.Namely, the nonvolatile semiconductor memory device, which has theplurality of nonvolatile memory elements MC<00> to MC<11> formed alongthe control electrodes CG<0> and CG<1> at the element forming regionisolated by the silicon oxide film 17 (STI filling material) which isthe element isolation film at the silicon substrate 11, is formed. Here,MC is a nonvolatile memory element, CG is a control electrode, FG is afloating electrode, and <nm> (nm: integer) expresses <row, column> in amatrix-form array. In FIG. 3, <nm> shows the four nonvolatile memoryelements MC<00> to MC<11>.

Further, the silicon oxide film 12 which is the gate insulating film isformed on the silicon substrate 11. The impurity diffusion layers 24-1,24-2, 24-3, which are to be the sources and the drains, are formed in adirection intersecting the control electrodes CG<0> and CG<1> so as toextend between the floating electrodes FG of the adjacent nonvolatilememory elements beneath the silicon oxide film 12. Moreover, thenonvolatile memory elements MC<00> to MC<11> respectively have thefloating electrodes FG<00> to FG<11>, and the control electrodes CG<0>and CG<1>.

The floating electrodes FG<00> to FG<11> are respectively formed withinthe regions of the nonvolatile memory elements MC<00> to MC<11>, and areformed of the polycrystalline silicon film 13 and the polycrystallinesilicon film 18 on the silicon oxide film 12 which is the gateinsulating film.

Further, ONO insulating films 19-1<0> and 19-1<1> which will be theinterelectrode insulating films are formed between the floatingelectrodes FG<00> to FG<11> and the control electrodes CG<0> and CG<1>.

On the other hand, the control electrode CG is structured from thepolycrystalline silicon film 20 and the WSi film 21. Namely, the controlelectrode CG<0> is formed above the floating electrodes FG<00> andFG<01> via the interelectrode insulating film 19-1<0>.

In the same way, the control electrode CG<1> is formed above thefloating electrodes FG<10> and FG<11> via the interelectrode insulatingfilm 19-1<1>.

Further, the space between the floating electrodes FG<00> and FG<01>which are adjacent along the control electrode CG<0> serves as a groove18A<0>. In the same way, the space between the floating electrodesFG<10> and FG<11> which are adjacent along the control electrode CG<1>serves as a groove 18A<1>.

As shown in FIG. 1, the ONO insulating film 19-2 is formed in theinterior of the groove 18A, and is formed so as to completely bury thegroove 18A which is between the floating electrodes 18 adjacent alongthe control electrode CG. For example, the ONO insulating film 19-2<0>is formed in the interior of the groove 18A<0>, and in the same way, theONO insulating film 19-2<1> is formed in the interior of the groove18A<1>.

By using the structure described above, the interelectrode insulatingfilm ONO insulating film 19-1 completely enters and fills in theinterior of the groove 18A. Accordingly, there is no case in which thecontrol electrode CG formed above the interelectrode insulating film ONOinsulating film 19-1 enters the interior of the groove 18A.

Next, with respect to operations of the respective elements, an exampleof the nonvolatile memory element MC<11> will be described.

The writing operation will be described. First, the silicon substrate 11is made to have ground potential. Further, a high voltage is appliedbetween the impurity diffusion layer 24-2 and the impurity diffusionlayer 24-3 which are to be the source and drain regions. For example,given that the impurity diffusion layer 24-2 is a source region and theimpurity diffusion layer 24-3 is a drain region, ground potential isapplied to the impurity diffusion layer 24-2 which is the source region,and a predetermined high potential is applied to the impurity diffusionlayer 24-3 which is the drain region.

Further, when the high potential is applied to the control electrodeCG<1>, a hot electron generated by the high electric potential appliedbetween the source and the drain, i.e., the impurity diffusion layers24-2 and 24-3 is injected in the floating electrode FG<11>. Or, FNcurrent is generated by the high voltage of the control electrode CG<1>,and electrons are injected in the floating electrode FG<11>.

In this way, the nonvolatile memory element MC<11> is selectivelywritten. Further, the electrons injected in the floating electrodeFG<11> are maintained as is. Therefore, written information ismaintained without a rewriting operation.

Next, reading operations will be described. First, the silicon substrate11 is made to have ground potential. Further, the impurity diffusionlayer 24-2 which will be the source region is made to have groundpotential. Moreover, an electric potential is applied to the impuritydiffusion layer 24-3 which will be the drain region. Next, a voltage isapplied to the control electrode CG<1>. At this time, assuming thatelectrons are injected in the floating electrode <11> of the nonvolatilememory element MC<11>, it is difficult for a channel to be formedbetween the source and the drain, and the threshold voltage becomeshigh. Namely, the memory element MC<11> is in the OFF-state, and currentdoes not flow between the impurity diffusion layers 24-2 and 24-3 whichare the source and the drain.

On the other hand, supposing that electrons are not injected in thefloating electrode <11>, a channel is easily formed between the sourceand the drain, and current flows therebetween, and the memory elementMC<11> becomes the ON-state. In this way, information written in thememory element MC<11> is read by reading the presence/absence of currentat the drain region of the nonvolatile memory element MC<11>, i.e., theimpurity diffusion layer 24-3, by a sense amplifier (not shown) or thelike which is connected thereto.

Next, the erasing operation will be described. The erasing operation isbatch-erasing with respect to all of the nonvolatile memory elementsMC<00> to MC<11>. Namely, a positive potential is applied to theimpurity diffusion layer 24 which is all of the drain regions and thesource regions. Moreover, a negative potential is applied to all of thecontrol electrodes CG<0> and CG<1>. As a result, the hold electrons areextracted from all of the floating electrodes FG<00> to FG<11>, andstored information of the nonvolatile memory elements MC<00> to MC<11>is erased. The above operations are in the same for the other thenonvolatile memory elements MC<00>, MC<01> as well, and MC<10>.

As described above, in the interior of the groove 18A which will be thegroove of the floating electrode FG which is adjacent along the controlelectrode CG, the ONO insulating film 19-2 is formed so as to completelyembed the groove. By using the structure as described above, theinterelectrode insulating film ONO insulating film 19-1 completelyenters the interior of the groove 18A, and the groove 18A is filled up.Accordingly, there is no case in which the control electrode CG formedabove the interelectrode insulating film ONO insulating film 19-1 entersthe interior of the groove 18A. In accordance therewith, it is possibleto eliminate cases in which the electrons injected in the floatingelectrode FG after the writing operation leak out to the controlelectrode CG due to the electric field convergence of a floatingelectrode corner portion 25. Namely, the electric charge maintainingcharacteristic can be improved.

In this way, in accordance with this embodiment, regardless of how widethe groove 18A is, the control electrode 20 does not hang down withinthe groove 18A as in the prior art. Therefore, the occurrence of theconvergence of electric fields with the floating electrode 18 can beprevented in advance. Accordingly, the electric charge maintainingcharacteristic of the nonvolatile memory element is markedly improved.

Further, in the embodiment shown in FIGS. 1 to 3, the device can bemanufactured by a method in which the groove insulating film 19-2filled-in the groove 18A is formed first, and thereafter, theinterelectrode insulating film 19-1 formed between the floatingelectrode 18 and the control electrode 20 is deposited. However, whenthe groove insulating film 19-2 and the interelectrode insulating film19-1 are formed of the same ONO films, it is possible to form bothsimultaneously.

On the other hand, the width of the groove 18A is a factor determiningthe interval between the two nonvolatile memory elements. If an attemptis made to dispose the nonvolatile memory elements at a high density ina limited area, the width of the groove 18A becomes narrow of necessity.

In such a case, in order to sufficiently exhibit the effects of thepresent embodiment, it is preferable that the width dF of the groove 18Aand the film thickness dONO of the interelectrode insulating film 19-1satisfy the following conditions. Those conditions will be described byusing FIG. 4.

FIG. 4 is a graph expressing the dependency of the groove width dF/thefilm thickness dONO with respect to an electric charge maintainingcharacteristic defective rate. Here, the groove width dF is the intervalof the groove 18A between the adjacent floating electrodes 18, and thefilm thickness dONO is the film thickness of the interelectrodeinsulating film 19-1 deposited between the polycrystalline silicon film20 and the polycrystalline silicon film 18.

As shown in FIG. 4, for example, in a conventional nonvolatilesemiconductor memory element having a structure as shown in FIG. 17,groove width dF/film thickness dONO=about 4. Accordingly, an electriccharge maintaining characteristic defective rate of about 8% arises.

On the other hand, in the present embodiment, when the groove insulatingfilm 19-2 and the interelectrode insulating film 19-1 are deposited byusing the same materials at one time, it can be understood from FIG. 4that it is preferable that groove width dF/film thickness dONO<1.6. Inthis case, the electric charge maintaining characteristic defective ratebecomes substantially 0%, and an extremely fine electric chargemaintaining characteristic is shown.

The relationship shown by the inequality groove width dF/film thicknessdONO<1.6 is a condition in which the groove 18A having the groove widthdF can be filled with the same insulating film by using an insulatingfilm having the film thickness dONO.

Namely, the film thickness in the groove width direction deposited inthe groove 18A generally depends on the type of the deposited insulatingfilm. This is because the film thickness in the groove width directiondeposited in the groove 18A becomes about 1.6 times the film thicknessdONO which is the interelectrode film insulating film 19-1 depositedbetween the floating electrode 18 and the control electrode 20. Thereason for this is that the film thickness of the inter-grooveinsulating film 19-2 deposited at the side surface of the floatingelectrode 18 is about 0.8 times the film thickness of the interelectrodeinsulating film 19-1 deposited between the polycrystalline silicon film18 and the polycrystalline silicon film 20.

On the other hand, when the interelectrode insulating film 19-1 isdeposited at the side surface of the groove 18A in an ideal state,because the film thickness becomes the same as the thickness depositedon the top surface of the floating electrode layer 18, it can beconsidered that the groove width dF becomes about 2.0 times the filmthickness dONO. However, when the interelectrode insulating film 19-1 isactually deposited under this condition, the groove is not completelyfilled up, and a slight cavity arises on the surface of theinterelectrode insulating film 19-1. As a result, the control electrodeenters the interior of the groove 18A as in the prior art, and electricfield convergence arises at the floating electrode corner portion. As aresult, the problem of deterioration of the electric charge maintainingcharacteristic due to electric field convergence cannot be solved.

However, when the floating groove width dF is less than 1.6 times thefilm thickness dONO, the interior of the groove 18A is completely filledwith, for example, the ONO insulating film 19, and the control electrode20 entering the groove 18A can be completely avoided. As a result, thecontrol electrode 20 does not cover the floating electrode cornerportion 25, and the device becomes a structure in which it is difficultfor electric field convergence to arise, and the electric chargemaintaining characteristic is improved.

Moreover, by satisfying this condition, the effect that dispersion ofthe distribution of the threshold value of each cell, i.e., eachnonvolatile memory element, is suppressed, can be anticipated. Namely,because the radius of curvature of the floating electrode corner portionat the side facing the control electrode differs for each cell, if thecorner portion is used for holding electric charges, the speed ofwriting/erasing varies for each cell. Therefore, dispersion of thethreshold distribution of the respective cells arises. However, in thepresent embodiment, the reason for this is that dispersion among cellsis reduced because the floating electrode corner portion 25 is not usedfor maintaining electric charges, and only the flat insulating film isused for writing/erasing.

Note that, in the present embodiment, a case in which the ONO insulatingfilm is used as the interelectrode film and the inter-groove insulatingfilm is shown. However, provided that it is an insulating film, the sameeffects can be obtained even if, for example, another insulating filmsuch as an oxide film, a silicon nitride film, or the like is used.

Hereinafter, an example of the manufacturing process of the nonvolatilesemiconductor memory device of the embodiment shown in FIGS. 1 to 3 willbe described with reference to FIGS. 5A to 5D, and 6A to 6E.

First, in FIGS. 5A and 6A, the silicon oxide film 12 is formed so as tohave a thickness of about 10 nm by being heated in, for example, an O₂atmosphere to 800° C., on the main surface of the silicon substrate 11.Next, for example, by a low pressure CVD method, the polycrystallinesilicon film 13 of about 60 nm which will be floating electrode, asilicon nitride film 14 of about 100 nm, and a silicon oxide film 15 ofabout 150 nm are deposited. Next, a desired pattern is formed by using aphotoresist by normal light etching, and the silicon oxide film 15 andthe silicon nitride film 14 are processed by using the pattern as a maskby an RIE method. Next, the silicon substrate is exposed to O₂ plasma,and the photoresist is eliminated, and the polycrystalline silicon film13 is processed by using the silicon oxide film 15 as a mask.

Next, in FIGS. 5B and 6B, the silicon oxide film 12 and the siliconsubstrate 11 are processed by using the silicon oxide film 15 as a mask,and the groove 17A is formed in the silicon substrate 11. Next, byheating in an O₂ atmosphere to about 1000° C., the silicon oxide film 16of about 6 nm is formed at the external wall of the groove 17A. Next,the silicon oxide film 17 of about 600 nm which will be the STI fillingmaterial is deposited by an HDP (high density plasma) method.

Next, in FIGS. 5C and 6C, the silicon oxide film 17 is flattened by aCMP (chemical mechanical polishing) method, and is heated in a nitrogenatmosphere to about 900° C. Moreover, the structure is immersed forabout 10 sec in a buffered HF solution, and the silicon nitride film 14is eliminated by phosphating at about 150° C. Next, the silicon oxidefilm 17 is etched at about 20 nm by a dilute HF solution.

Moreover, the polycrystalline silicon film 18 which is made to be afloating electrode due to phosphorus being added by the low pressure CVDmethod is deposited. Further, the polycrystalline silicon film 18 isprocessed by the RIE method by using the mask of the photoresist at thesubstantially central portion of the top surface of the silicon oxidefilm 17, and the groove 18A is formed.

Moreover, in FIGS. 5D and 6D, the ONO insulating films 19-1 and 19-2(three-layer films of a silicon oxide film of about 5 nm, a siliconnitride film of about 5 nm, and a silicon oxide film of about 5 nm), thepolycrystalline silicon film 20 of about 100 nm which will be thecontrol electrode and to which phosphorus is added, the WSi film 21 ofabout 100 nm, and the silicon oxide film 22 of about 200 nm aredeposited by the low pressure CVD method. Next, the photoresist ispatterned in a desired form by a photolithography method, and thesilicon oxide film 22 is processed by using the patterned photoresist asa mask by, for example, the RIE method.

Next, in FIG. 6E, by using the silicon oxide film 22 as a mask, the WSifilm 21, the polycrystalline silicon film 20, the ONO insulating films19-1 and 19-2, the polycrystalline silicon film 18, the polycrystallinesilicon film 13 are successively processed by, for example, the RIEmethod. Moreover, the impurity diffusion layers 24-1, 24-2, and 24-3which will be the source/drain regions are formed in a self-alignedmanner by using the processed control electrode and the aforementionedpattern of the silicon oxide film 17 which will be the STI fillingmaterial as masks. Moreover, silicon oxide films 23 are formed at theside walls of the respective nonvolatile memory elements MC by heatingin an O₂ atmosphere to about 1000° C.

In accordance with the above-described manufacturing processes, thenonvolatile memory elements MC<00> to MC<11> are formed.

As shown in FIG. 5D, the interior of the groove 18A<1> between thefloating electrodes is filled with the ONO insulating film 19-2<1>.Therefore, the device is structured such that the polycrystallinesilicon film 20 and the WSi film 21 structuring the control electrodeCG<1> cannot enter the interior of the groove 18A<1>. Thus, electricfield convergence at the floating electrode corner portion 25 does notarise, and the electric charge maintaining characteristic is improved.

Further, the manufacturing method according to the present embodiment isa process in which the ONO insulating film 19-1 which is theinterelectrode insulating film of the control electrodes CG<0>, CG<1>and the floating electrodes FG<00> to FG<11>, and the ONO insulatingfilm 19-2 which is the groove insulating film filled in the groove18A<0> and groove 18A<1> use the same insulating film, and aresimultaneously deposited. At this time, the groove width dF and the filmthickness dONO are formed so as to satisfy the relational expressionshown in this embodiment, which is groove width dF/film thicknessdONO<1.6.

Therefore, because the interiors of the groove 18A<0> and the groove18A<1> can be filled with the insulating film 19-2, electric fieldconvergence does not arise with respect to the control electrode at thefloating electrode corner portion 25. Accordingly, the electric chargemaintaining characteristic is improved, and the electric chargemaintaining defective rate can be made to be substantially 0%.

Further, because the interval between the electrodes and the groove canbe filled by using the same insulating film in this way, themanufacturing costs can be reduced, and the manufacturing speed can beimproved.

As described above, this is a process in which the groove insulatingfilms filled in the interelectrode insulating film and the groove aremanufactured at one time by using the same insulating film. However, inorder to fill the groove 18A<0> and the groove 18A<1>, it is possiblethat an insulating film such as an oxide film, a silicon nitride film,or the like is deposited first, and the entire surface thereof is etchedby the RIE method, or the insulating films other than an inter floatingelectrode film are eliminated by the CMP method, and thereafter, theinterelectrode insulating films of the control electrodes CG<0>, CG<1>and the floating electrodes FG<00> to FG<11> are deposited by using aninsulating film different therefrom.

In this way, when the interelectrode film and the groove insulating filmare deposited in separate processes, the electric charge maintainingratio is not reduced even when there is a the large groove width whichdoes not satisfy the relational expression of the groove width dF andthe film thickness dONO between the electrodes shown in theabove-described embodiment. In this way, in the process in which theinsulating films are separately deposited, because the interiors of thegroove 18A<0> and the groove 18A<1> can be completely filled with theinsulating films regardless of the widths of the grooves, the controlelectrode does not enter the grooves, and electric field convergencedoes not arise at the floating electrode corner portion 25 facing thecontrol electrode. Therefore, the electric charge maintainingcharacteristic can be improved.

SECOND EMBODIMENT

A second embodiment according to the present invention will be describedby using FIGS. 7, and 8A to 8C. In the descriptions of the followingembodiments, descriptions of portions which are the same as in the firstembodiment will be omitted.

FIG. 7 is a cross-sectional structural view of the plurality ofnonvolatile semiconductor memory device formed along the wiringlongitudinal direction of the control electrodes CG (the polycrystallinesilicon film 20 and the WSi film 21) so as to correspond to FIG. 1.FIGS. 8A to 8C are process views for explanation of one example of themethod of manufacturing the nonvolatile semiconductor memory deviceshown in FIG. 7.

As shown in FIG. 7, the groove 18A whose groove width dF is, forexample, about 80 nm is formed at the substantially central portion ofthe top surface of the silicon oxide film 17 which is the STI fillingmaterial. The silicon oxide film 31 having a low dielectric constant isformed at the interior of the groove 18A.

An alumina (Al₂O₃) film 32 is formed along the longitudinal direction ofthe control electrode CG between the polycrystalline silicon film 18 andthe polycrystalline silicon film 20. The alumina film 32 is aninsulating material having a dielectric constant which is higher than atleast the dielectric constant of the silicon oxide film 31 having theabove-described low dielectric constant.

In this way, in the present embodiment, the insulating film formed inthe interior of the groove 18A and the insulating film formed betweenthe floating electrode FG and the control electrode CG are formed ofdifferent materials, and are formed such that the dielectric constantsof the respective insulating films differ from one another.

First, due to the insulating film formed in the interior of the groove18A and the insulating film formed between the floating electrode FG andthe control electrode CG being separately formed, even if the groovewidth is broad, the interior of the groove 18A can be completely filledwith the insulating film. Therefore, the control electrodes CG do notenter the interior of the groove 18A. As a result, in the same way as inthe first embodiment, convergence of the electric field at the floatingelectrode corner portion 25 can be avoided, and the electric chargemaintaining characteristic can be improved.

Furthermore, the dielectric constants of the respective insulating filmsare formed so as to differ from each other. Namely, the silicon oxidefilm 32 which is an insulating material whose dielectric constant is lowis formed so as to be filled in the groove 18A. Therefore, a datainterference effect due to the capacitive coupling between the floatingelectrodes FG which are adjacent along the control electrodes CG can besuppressed to a minimum. Here, the data interference effect due to thecapacitive coupling between the floating electrodes FG means the effectin which the threshold voltages of the adjacent floating electrodes FGare affected in accordance with the electrical states of the floatingelectrodes FG. For example, it means that the threshold voltages of theadjacent floating electrodes FG are affected in accordance with whetherelectrons are injected in the floating electrodes FG or not.Accordingly, when the effect is large, the ability to control of thethreshold voltages of the respective nonvolatile memory elements MCdeteriorates. However, the silicon oxide film 32 which is an insulatingmaterial whose dielectric constant is low is filled in the groove 18A.Therefore, the electrical effect between the adjacent floatingelectrodes FG can be suppressed to a minimum. As a result, theabove-described data interference effect can be suppressed to a minimum,and the reliabilities of the respective nonvolatile memory elements MCcan be improved.

Moreover, the insulating film formed between the polycrystalline siliconfilm 18 and the polycrystalline silicon film 20 is formed of the aluminafilm 32 which is an insulating material whose dielectric constant ishigh. Accordingly, the capacitive coupling between the floatingelectrode FG and the control electrode CG becomes high. As a result, thecontrol voltage at the time of writing and reading which is applied tothe control electrode CG can be reduced.

Note that the aforementioned groove insulating film formed in theinterior of the groove 18A is preferably an insulating material whosedielectric constant is as low as possible. Accordingly, the grooveinsulating film is preferably formed of a silicon oxide film formed bybeing deposited, for example, by the coating method, or the like, morethan a silicon oxide film formed by normal thermal oxidation. However,if the material is a material whose dielectric constant is low, theembodiment is not limited to the silicon insulating film 31, and otherinsulating materials can be applied to the present embodiment.

As the insulating material formed between the polycrystalline siliconfilm 20 and the polycrystalline silicon film 18, in addition to theAl₂O₃ (alumina) film 32, for example, Ta₂O₅ (tantalum oxide) film andthe like can be applied to the invention. In consideration of the factthat the device must have a sufficient insulation performance in orderfor the electric charges of the floating electrode FG to not leak, theAl₂O₃ (alumina) film 32 is more preferable in the present technique.Moreover, in consideration of the fact that it suffices for theinsulating material to be a high dielectric constant film and for theleakage current to be less than or equal to a given value, for example,a silicon nitride film or the like as well can be applied to the presentembodiment. In this case, a silicon nitride film using a depositingmethod in which there igroovetle leakage current using, for example, theJVD (jet vapor deposition) method, or the like, is applied to thepresent embodiment. Further, as compared with a case in which thesesingle-layer films whose dielectric constants are high are used, amulti-layer structure film such as an ONO insulating film (oxidefilm/nitride film/oxide film) or the like can be used, although thecapacitive coupling between the floating electrode FG and the controlelectrode CG becomes small.

Hereinafter, one example of the method of manufacturing the nonvolatilesemiconductor memory device shown in FIG. 7 will be described by usingFIGS. 8A to 8C.

First, in FIG. 8A, the silicon oxide film 12, the polycrystallinesilicon film 13, the silicon nitride film 14, the silicon oxide film 15,the silicon oxide film 16, and the silicon oxide film 17 which is theSTI filling material are formed on the main surface of the siliconsubstrate 11 by the same method as in the first embodiment.

Next, in FIG. 8B, the polycrystalline silicon film 18, which is made tobe the floating electrode due to phosphorus being added by the lowpressure CVD method, is deposited. Moreover, the polycrystalline siliconfilm 18 is processed by using the mask of the photoresist by the RIEmethod, and the groove 18A is formed at the substantially centralportion of the top surface of the silicon oxide film 17. At this time,the groove width of the groove 18A is, for example, about 80 nm.Moreover, the silicon oxide film 31 having a low dielectric constant isformed in the interior of the groove 18A by using, for example, acoating method.

Subsequently, in FIG. 8C, the alumina film 32 is formed by, for example,the CVD method. Thereafter, the nonvolatile semiconductor memory deviceshown in FIG. 7 can be formed by the same manufacturing processes as inthe first embodiment.

THIRD EMBODIMENT

A third embodiment according to the present invention will be describedby using FIGS. 9, and 10A to 10C.

FIG. 9 is a cross-sectional structural view of the plurality ofnonvolatile semiconductor memory device formed along the wiringlongitudinal direction of the control electrodes CG. FIGS. 10A to 10Care process views for explanation of one example of the method ofmanufacturing the nonvolatile semiconductor memory device shown in FIG.9.

As shown in FIG. 9, the groove 18A whose groove width dF is, forexample, about 10 nm is formed at the substantially central portion ofthe top surface of the silicon oxide film 17 which is the STI fillingmaterial. A silicon oxide film 33 having a low dielectric constant isformed in the interior of the groove 18A. Moreover, the same siliconoxide film 33 is formed so as to have a thin film thickness between thepolycrystalline silicon film 20 and the polycrystalline silicon film 18,and both are formed so as to be integrated. Here, the film thickness ofthe silicon oxide film 33 formed between the polycrystalline siliconfilm 20 and the polycrystalline silicon film 18 is, for example, about 5to 6 nm.

An alumina film 34 is formed on the top surface of the above-describedsilicon oxide film 33. In the same way as described above, the aluminafilm 34 is an insulating material having a high dielectric constant.

The silicon oxide film 33 is formed so as to have a thin film thicknessin the interior of the groove 18A and between the polycrystallinesilicon film 20 and the polycrystalline silicon film 18, and both areformed so as to be integrated. In this way, the interior of the groove18A is filled with the silicon oxide film 33 which is an insulating filmwhose dielectric constant is low. As a result, the electric chargemaintaining characteristic can be improved, and the data interferenceeffect between the above-described floating electrodes FG can be reducedto a minimum.

The low dielectric constant silicon oxide film 33 is formed so as tohave a thin film thickness between the polycrystalline silicon film 20and the polycrystalline silicon film 18 as well. As a result,convergence of the electric field at the floating electrode cornerportion 25 can be avoided, and the electric charge maintainingcharacteristic can be improved more.

The alumina film 34 having a high dielectric constant is formed on thetop surface of the above-described silicon oxide film 33 formed so as tobe thin. As a result, due to the capacitive coupling between thefloating electrode FG and the control electrode CG being made to behigh, the control voltage applied to the control electrode CG at thetime of writing and reading can be reduced.

Furthermore, the film thickness of the silicon oxide film 33 formedbetween the polycrystalline silicon film 20 and the polycrystallinesilicon film 18 is formed so as to be thinner than the film thickness ofthe alumina film 34. As a result, the above-described effect forreducing the operational voltage and the above-described effect forimproving the electric charge maintaining characteristic can be achievedtogether.

Moreover, the film thickness of the silicon oxide film 33 formed betweenthe polycrystalline silicon film 20 and the polycrystalline silicon film18 is, for example, about 5 to 6 nm. Accordingly, even when the width dFof the groove 18A is an extremely small dimension which is, for example,about 10 nm, the interior of the groove 18A can be filled up. As aresult, the nonvolatile memory elements can be arranged at a highdensity, and the electric charge maintaining characteristic is improved,so that the data interference effect between the adjacent floatingelectrodes FG can be reduced to a minimum. In this way, this is astructure which is effective for extremely small dimensions as well.

Note that, in the same way as described above, the silicon insulatingfilm 33 is preferably an insulating material whose dielectric constantis as low as possible. A silicon oxide film formed by being deposited,for example, by the coating method, or the like, is applicable. Further,if the material is a material whose dielectric constant is low, otherinsulating materials are also applicable.

In the alumina film 34 formed on the top surface of the silicon oxidefilm 33 formed so as to be thin, in the same way, for example, a Ta₂O₅(tantalum oxide) film, a silicon nitride film, an ONO insulating film,or the like can be used.

Hereinafter, one example of the method of manufacturing the nonvolatilesemiconductor memory device shown in FIG. 9 will be described by usingFIGS. 10A to 10C.

First, in FIG. 10A, by the same method as in the first embodiment, onthe main surface of the silicon substrate 11, after the groove 17A whichwill be an element isolation region is formed, the silicon oxide film12, the polycrystalline silicon film 13, the silicon nitride film 14,the silicon oxide film 15, the silicon oxide film 16, and the siliconoxide film 17 which is the STI filling material are successively formed.

Next, in FIG. 10B, the silicon oxide film 17 is flattened by the CMPmethod, and is heated in a nitrogen atmosphere to about 900° C. Further,the silicon oxide film 17 is immersed for about 10 sec in a buffered HFsolution, and the silicon nitride film 14 is eliminated by phosphatingat about 150° C. Next, the silicon oxide film 17 is etched at about 20nm in a dilute HF solution. Moreover, the polycrystalline silicon film18 which is made to be a floating electrode due to phosphorus beingadded by the low pressure CVD method is deposited. Furthermore, thepolycrystalline silicon film 18 is processed by the RIE method by usinga mask of a photoresist, and the groove 18A is formed at thesubstantially central portion of the top surface of the silicon oxidefilm 17. At this time, the groove width of the groove 18A is, forexample, 10 nm. In addition, in the groove 18A and on the top surface ofthe polycrystalline silicon film 18, by using, for example, the CVDmethod, the silicon oxide film 33 having a low dielectric constant isformed simultaneously without the process for filling the in the groove18A.

Next, in FIG. 10C, the alumina film 34 is formed by, for example, theCVD method. Therefore, the nonvolatile semiconductor memory device shownin FIG. 9 can be formed by the same manufacturing processes as in thefirst embodiment.

In the method of manufacturing according to the embodiment, by using,for example, the CVD method, the silicon oxide film 33 having a lowdielectric constant is formed in the groove 18A and on the top surfaceof the polycrystalline silicon film 18, simultaneously with the fillingin the groove 18A. Accordingly, the process of separately filling in thegroove 18A can be omitted.

Note that, in the first to third embodiments, the floating electrodes FGare formed of the polycrystalline silicon film 13 and thepolycrystalline silicon film 18 whose both ends project up to thegrooves 18A on the silicon oxide film 17 formed on the top surfacethereof. In this way, due to the polycrystalline silicon film 18projecting up to the grooves 18A, the surface area facing the controlelectrode CG can be made to be large. As a result, the capacitivecoupling ratio can be made large.

FOURTH EMBODIMENT

A fourth embodiment according to the present invention will be describedby using FIG. 11, and FIGS. 12A to 12C.

FIG. 11 is a cross-sectional structural view of the plurality ofnonvolatile semiconductor memory device formed along the wiringlongitudinal direction of the control electrodes CG. FIGS. 12A to 12Care process views for explanation of one example of the method ofmanufacturing the nonvolatile semiconductor memory device shown in FIG.11.

As shown in FIG. 11, the polycrystalline silicon film 13 which is thefloating electrode FG is formed on the silicon oxide film 12 at theelement region. The floating electrode FG is formed of only thispolycrystalline silicon film 13. Moreover, a low dielectric constantsilicon oxide film 35 which is the STI filling material is formed in theinterior of the groove 17A which is the element isolation region. Thewidth of the groove 17A which is the element isolation region is, forexample, about 60 nm. Moreover, an alumina film 36 is formed on the topsurfaces of the above-described polycrystalline silicon film 13 and thesilicon oxide film 35. In the same way as described above, the aluminafilm 36 is an insulating material having a high dielectric constant.

As shown in FIG. 11, the floating electrode FG is formed of only thepolycrystalline silicon film 13. On the other hand, the floatingelectrode FG according to the above-described first to third embodimentsis formed of the polycrystalline silicon film 18 whose both ends projectup to the groove 18A of the silicon oxide film 16 formed on the topsurface thereof. However, if the interval of the nonvolatile memoryelements CM which are adjacent along the control electrode CG is madesmall by miniaturization, there are cases in which it is difficult touse a structure as described above. This is because, if theabove-described interval becomes small, there are cases in which theinsulation performance between the nonvolatile memory elements CM whichare adjacent along the control electrode CG cannot be sufficientlyensured.

However, in the present embodiment, the polycrystalline silicon film 13is isolated by the low dielectric constant silicon oxide film 35 whichis the element region, and the polycrystalline silicon film 13 does notproject on the top surface of the silicon oxide film 35. Therefore, evenwhen the interval of the adjacent nonvolatile memory elements MC becomessmall, the insulation between the adjacent nonvolatile memory elementsCM can be sufficiently ensured.

The low dielectric constant silicon oxide film 35 which is the STIfilling material is formed in the interior of the groove 17A which willbe an element isolation region. Therefore, the coupled capacities, notonly between the adjacent floating electrodes, but also between thefloating electrodes and the source/drain regions (not shown) which areactive regions, and between the source region and the drain region (notshown), can be reduced. As a result, the above-described interferenceeffect between the adjacent nonvolatile memory elements can be reduced.

Note that, in the same way as described above, the silicon oxide film 35with a low dielectric constant is preferably an insulating materialwhose dielectric constant is as low as possible. A silicon oxide filmformed by being deposited, for example, by the coating method, or thelike, is applicable. Moreover, if the material is a material whosedielectric constant is low, other insulating materials are alsoapplicable.

Moreover, in the alumina film 36 formed on the top surface of thesilicon oxide film 35, in the same way, an insulating material whosedielectric constant is high is preferable. Accordingly, for example, aTa₂O₅ (tantalum oxide) film, a silicon nitride film, an ONO insulatingfilm, or the like can be used.

Hereinafter, one example of the method of manufacturing the nonvolatilesemiconductor memory device shown in FIG. 11 will be described by usingFIGS. 12A to 12C.

First, in FIG. 12A, by the same method as in the first embodiment, onthe main surface of the silicon substrate 11, after the groove 17A whichwill be an element isolation region is formed, the silicon oxide film12, the polycrystalline silicon film 13, the silicon nitride film 14,the silicon oxide film 15, and the silicon oxide film 16, aresuccessively formed. Thereafter, the low dielectric constant siliconoxide film 35 which is the STI filling material is formed by, forexample, the coating method (or the CVD method).

Next, in FIG. 12B, the silicon oxide film 35 is flattened up to thesurface of the silicon nitride film 14 by, for example, the CMP method,and is heated in a nitrogen atmosphere to about 900° C. Moreover, thesilicon nitride film 14 is immersed in a buffered HF solution, and thesilicon nitride film 14 is eliminated by phosphating at about 150° C.Next, the silicon oxide film 35 with a low dielectric constant iswithdrawn by a dilute HF solution.

Subsequently, in FIG. 12C, the alumina film 36 is formed by, forexample, the CVD method on the top surfaces of the polycrystallinesilicon film 13 and the silicon oxide film 35 with a low dielectricconstant. Hereinafter, the nonvolatile semiconductor memory device shownin FIG. 11 can be formed by the same manufacturing processes as in thefirst embodiment.

In the manufacturing method according to the embodiment, the fillingmaterial and the insulating film isolating the adjacent floatingelectrodes FG are simultaneously formed by the silicon oxide film 35with a low dielectric constant. Therefore, the manufacturing processesare simplified, and the manufacturing cost can be reduced.

Further, the floating electrode FG is formed of only the polycrystallinesilicon film 13. Therefore, the manufacturing processes are simplified,and the manufacturing cost can be reduced.

FIFTH EMBODIMENT

A fifth embodiment according to the present invention will be describedby using FIGS. 13, and 14A to 14D.

FIG. 13 is a cross-sectional structural view of the plurality ofnonvolatile semiconductor memory device formed along the wiringlongitudinal direction of the control electrodes CG. FIGS. 14A to 14Dare process views for explanation of one example of the method ofmanufacturing the nonvolatile semiconductor memory device shown in FIG.13.

As shown in FIG. 13, the silicon oxide film 35 with a low dielectricconstant is formed in the interior of the groove 17A which is theelement region isolation region. In the same way as described above, thesilicon oxide film 35 is an insulating material having a low dielectricconstant. A polycrystalline silicon film 37 whose both end portionsproject along the direction of the control electrode CG in the interiorof the silicon oxide film 35 is formed on the surface of thepolycrystalline silicon film 13. The floating electrode is formed of thetwo layers of the polycrystalline silicon film 37 and thepolycrystalline silicon film 13. Moreover, the alumina film 36 is formedalong the direction of the control electrode CG on the top surfaces ofthe silicon oxide film 35 with a low dielectric constant and thepolycrystalline silicon film 37. In the same way as described above, thealumina film 36 is an insulating material having a high dielectricconstant.

The above-described polycrystalline silicon film 37 is formed so as tobe a form in which both end portions thereof project along the directionof the control electrode CG in the interior of the silicon oxide film 35on the surface of the polycrystalline silicon film 13. Therefore, thesurface area facing the control electrode CG can be made to be large. Asa result, due to the capacitive coupling ratio being increased, thethreshold voltage applied to the control electrode CG can be reduced.

The silicon oxide film 35 with a low dielectric constant is formed inthe interior of the groove 17A which will be the element regionisolation region. Accordingly, the coupled capacity of the adjacentfloating electrodes FG can be reduced.

The alumina film 36 having a high dielectric constant is formed alongthe direction of the control electrode CG on the surfaces of the siliconoxide film 35 and the polycrystalline silicon film 37. As a result, dueto the coupled capacity between the control electrode CG and thefloating electrode FG being increased, the threshold voltage applied tothe control electrode CG can be reduced.

Note that, in the same way as described above, the silicon oxide film 35with a low dielectric constant is preferably an insulating materialwhose dielectric constant is low, and a silicon oxide film formed bybeing deposited, for example, by the coating method, or the like, isapplicable. Moreover, if the material is a material whose dielectricconstant is low, other insulating materials are also applicable.

Moreover, in the above-described alumina film 36 formed on the topsurface of the silicon oxide film 35, in the same way, an insulatingmaterial whose dielectric constant is high is preferable. Accordingly,for example, a Ta₂O₅ (tantalum oxide) film, a silicon nitride film, anONO insulating film, or the like can be used.

Hereinafter, one example of the method of manufacturing the nonvolatilesemiconductor memory device shown in FIG. 13 will be described by usingFIGS. 14A to 14D.

First, in FIG. 14A, by the same method as in the first embodiment, onthe main surface of the silicon substrate 11, after the groove 17A whichwill be an element isolation region is formed, the silicon oxide film12, the polycrystalline silicon film 13, the silicon nitride film 14,the silicon oxide film 15, and the silicon oxide film 16, aresuccessively formed. Thereafter, the low dielectric constant siliconoxide film 35 which will be the STI filling material is formed by, forexample, the coating method.

Next, in FIG. 14B, by using the silicon nitride film 14 as a stopper,the silicon oxide film 35 with a low dielectric constant is flattened tothe surface of the silicon nitride film 14 by, for example, the CMPmethod, and is heated in a nitrogen atmosphere to about 900° C. Further,the silicon nitride film 14 is immersed in a buffered HF solution, andthe silicon nitride film 14 is eliminated by phosphating at about 150°C.

Next, in FIG. 14C, the silicon oxide film 35 with a low dielectricconstant is isotropically made to withdraw by a dilute HF solution.

In addition, the polycrystalline silicon film 37 is formed so as to bedeposited on the entire surface by, for example, the CVD method.Moreover, the silicon oxide film 35 and the polycrystalline silicon film37 are flattened by, for example, the CMP method.

Next, in FIG. 14D, the alumina film 36 is formed by, for example, theCVD method on the top surfaces of the polycrystalline silicon 37 and thesilicon oxide film 35 with a low dielectric constant. Thereafter, thenonvolatile semiconductor memory device shown in FIG. 13 can be formedby the same manufacturing processes as in the first embodiment.

In the manufacturing method according to the embodiment, both endportions of the silicon oxide film 35 are eliminated such that thecentral portion of the silicon oxide film 35 remains. Further, thepolycrystalline silicon film 37 is formed so as to be deposited on theentire surface by, for example, the CVD method. Furthermore, the siliconoxide film 35 and the polycrystalline silicon film 37 are flattened by,for example, the CMP method. In this way, a structure in which both endsof the polycrystalline silicon film 37 project can be formed in aself-aligned manner. As a result, even when the width of the groove 17Aisolating the floating electrode FG is narrow, a structure in which thepolycrystalline silicon film 37 projects can be formed. As describedabove, due to the structure in which the polycrystalline silicon film 37projects, the capacitive coupling between the floating electrode FG andthe control electrode CG can be increased.

SIXTH EMBODIMENT

A sixth embodiment according to the present invention will be describedby using FIGS. 15, and 16A to 16D.

FIG. 15 is a cross-sectional structural view of the plurality ofnonvolatile semiconductor memory device formed along the wiringlongitudinal direction of the control electrodes CG. FIGS. 16A to 16Dare process views for explanation of one example of the method ofmanufacturing the nonvolatile semiconductor memory device shown in FIG.15.

As shown in FIG. 15, a top surface of a silicon oxide film 38 with a lowdielectric constant is formed so as to be higher than the top surface ofthe polycrystalline silicon film 18 in the interior of the groove 17Awhich will be the element region isolation region. The silicon oxidefilm 38 is an insulating material having a low dielectric constant. Analumina film 39 is formed along the direction of the control electrodeCG on the top surfaces of the low dielectric constant silicon oxide film38 and the polycrystalline silicon film 18. The alumina film 39 is aninsulating material having a high dielectric constant.

The top surface of the silicon oxide film 38 with a low dielectricconstant is formed so as to be higher than the top surface of thepolycrystalline silicon film 18 which is adjacent thereto in theinterior of the groove 17A which will be the element region isolationregion. Accordingly, the control electrode CG does not enter theinterior of the groove 17A. As a result, converging of the electricfield at the corner of the floating electrode can be avoided. Moreover,the silicon oxide film 38 is formed of a low dielectric constantinsulating film. Accordingly, the coupled capacity between the adjacentfloating electrodes FG can be reduced. In accordance with the structureof the silicon oxide film 38 as described above, the reliability of thenonvolatile memory element can be improved more. Therefore, even if thewidth of the groove 17A is, for example, less than or equal to about 100nm, it can be applied to the present embodiment.

Moreover, the alumina film 39 having a high dielectric constant isformed along the direction of the control electrode CG on the surfacesof the silicon oxide film 38 and the polycrystalline silicon film 18.Consequently, due to the coupled capacity between the control electrodeCG and the floating electrode. FG being increased, the voltage appliedto the control electrode CG can be reduced.

Note that, in the same way as described above, the silicon oxide film 38with a low dielectric constant is preferably an insulating materialwhose dielectric constant is low, and a silicon oxide film formed bybeing deposited, for example, by the coating method, or the like, isapplicable. Further, if the material is a material whose dielectricconstant is low, other insulating materials are also applicable.

Moreover, in the above-described alumina film 39 formed on the topsurface of the silicon oxide film 38, in the same way, an insulatingmaterial whose dielectric constant is high is preferable. Accordingly,for example, a Ta₂O₅ (tantalum oxide) film, a silicon nitride film, anONO insulating film, or the like can be used.

Hereinafter, one example of the method of manufacturing the nonvolatilesemiconductor memory device shown in FIG. 15 will be described by usingFIGS. 16A to 16D.

First, in FIG. 16A, by the same method as in the first embodiment, onthe main surface of the silicon substrate 11, after the groove 17A whichwill be an element isolation region is formed, the silicon oxide film12, the polycrystalline silicon film 13, the silicon nitride film 14,the silicon oxide film 15, and the silicon oxide film 16 aresuccessively formed. Thereafter, the low dielectric constant siliconoxide film 38 which is the STI filling material is formed by, forexample, the coating method.

Next, in FIG. 16B, by using the silicon nitride film 14 as a stopper,the silicon oxide film 38 with a low dielectric constant is flattened tothe surface of the silicon nitride film 14 by, for example, the CMPmethod, and is heated in a nitrogen atmosphere to about 900° C.Moreover, the silicon nitride film 14 is immersed in a buffered HFsolution, and the silicon nitride film 14 is eliminated by phosphatingat about 150° C.

Then, in FIG. 16C, the polycrystalline silicon film 18 is formed so asto be deposited on the entire surface by, for example, the CVD method.Moreover, by using the silicon oxide film 38 as a stopper, the siliconoxide film 38 and the polycrystalline silicon film 18 are flattened by,for example, the CMP method. One portion of the polycrystalline siliconfilm 18 is eliminated and is made become to hollow by, for example, RIEmethod. In this way, a structure in which the top surface of the siliconoxide film 38 is higher than the top surface of the polycrystallinesilicon film 18 is formed.

Subsequently, in FIG. 16D, the alumina film 39 is formed on the topsurfaces of the polycrystalline silicon 18 and the low dielectricconstant silicon oxide film 38 by, for example, the CVD method.Thereafter, the nonvolatile semiconductor memory device shown in FIG. 15can be formed by the same manufacturing processes in the firstembodiment.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1-22. (canceled)
 23. A nonvolatile semiconductor memory devicecomprising: a semiconductor substrate including a plurality of elementisolation grooves formed along a first direction on a main surface and aplurality of element regions respectively isolated by the elementisolation grooves; an element isolation insulating film formed in theelement isolation grooves, a top surface of the element isolationinsulating film being higher than a surface of the semiconductorsubstrate; a gate insulating film formed on the element regions of thesemiconductor substrate; a plurality of floating electrodes formed alonga second direction intersecting the first direction, with the elementisolation regions interposed in between, the top surface of the floatingelectrode being flush with a top surface of the element isolationinsulating film; interelectrode insulating films having a higherdielectric constant than the element isolation insulating film andformed along the second direction on the plurality of floatingelectrodes and the element isolation insulating film; and a controlelectrode formed along the second direction on the interelectrodeinsulating film.
 24. The device according to claim 23, wherein theinterelectrode insulating film is an alumina film.
 25. The deviceaccording to claim 23, wherein the interelectrode insulating film is atantalum oxide film.
 26. The device according to claim 23, wherein a topend portion of the element isolation insulating film has a taperedsurface and the floating electrodes have a greater width at a topsurface than at a bottom surface.
 27. A nonvolatile semiconductor memorydevice comprising: a semiconductor substrate including a plurality ofelement isolation grooves formed along a first direction on a mainsurface and a plurality of element regions respectively isolated by theelement isolation grooves; an element isolation insulating film formedin the element isolation grooves, a top surface of the element isolationinsulating film being higher than a surface of the semiconductorsubstrate; a gate insulating film formed on the element regions of thesemiconductor substrate; a plurality of floating electrodes formed alonga second direction intersecting the first direction, with the elementisolation insulating films interposed in between, the top surface of thefloating electrode being lower than a top surface of the elementisolation insulating film; interelectrode insulating films having ahigher dielectric constant than the element isolation insulating filmand formed along the second direction on the plurality of floatingelectrodes and the element isolation insulating film; and a controlelectrode formed along the second direction on the interelectrodeinsulating film.
 28. The device according to claim 27, wherein theinterelectrode insulating film is an alumina film.
 29. The deviceaccording to claim 27, wherein the interelectrode insulating film is atantalum oxide film.